The present invention relates to a semi-conductor device with a Test Element Group for estimating an interlayer dielectric, and particularly to a semiconductor device having a memory cell array in which a floating gate, an interlayer dielectric, and a control gate are sequentially formed.
When an interlayer dielectric formed between a floating gate and control gate is to be evaluated by the Test Element Group (hereunder called xe2x80x9cTEGxe2x80x9d), a TEG with a flat structure showed in FIG. 5 and a TEG with a floating gate transistor structure showed in FIG. 6 are generally used. FIG. 5A is a sectional view of the TEG with flat structure. FIG. 5B is a plan view of the TEG with flat structure. The TEG with flat structure includes a planar control gate 4 formed on a planar interlayer dielectric 3 that is formed on a planar floating gate 2. Electrodes 5 for estimating the interlayer dielectric 3 are formed on the control gate 4 and the floating gate 2 respectively. When the interlayer 3 is estimated by the TEG with flat structure, certain voltages are applied between the electrodes formed on the control gate and the floating gate 2 within a certain time for accelerated life estimation regarding the dielectric breakdown. In this case, the number of the interlayer dielectric included in the TEG for estimation of interlayer dielectric 3 is calculated by area converting according to an area of the interlayer dielectric 3 within a memory cell in a real semi-conductor. If interlayer dielectric 3 breakdown is occurred, the number of the interlayer dielectric breakdown is calculated by area converting similarly. Then according to the number of the interlayer dielectric breakdown, life estimation per bit of the interlayer dielectric 3 is examined.
FIG. 6A is a perspective sectional view of the TEG with floating gate transistor structure. FIG. 6B is a plan view of the TEG with floating gate transistor structure. The TEG with floating gate transistor structure includes an isolation 6, floating gate 2, interlayer dielectric 3, and control gate 4 that are sequentially formed on a semiconductor substrate 1 in this order. Electrodes 5 of estimating interlayer dielectric 3 are formed on the edge portions of the control gate 4 and the floating gate 2. The estimation of the interlayer dielectric using the TEG with floating gate transistor structure is similar to the estimation using the TEG with flat structure. The life estimation of interlayer dielectric 3 is examined by area converting.
However, a step of the floating gate 2, which is formed in a real semiconductor device, is not formed on an isolation 6 in the TEG with flat structure 30. Then the interlayer dielectric 3 of the TEG with flat structure 30 is formed planar. For this reason, even though interlayer dielectric 3 can be estimated itself, an effectiveness of the step of the interlayer dielectric 3 on the isolation 6 of the real semi-conductor device cannot be ascertained. Similarly, in the TEG with floating gate transistor structure 40, an effectiveness of the step of the interlayer dielectric 3 on the isolation 6 of a real semi-conductor device cannot be ascertained. The resistance component of the floating gate 2 is enlarged because of only one electrode used on the floating gate 2 for estimating the interlayer dielectric 3.
The life estimation of the interlayer dielectric 3 having a large area is examined by the TEG with flat structure 30 and by the TEG with floating gate transistor structure 40. In this case, the areas of the interlayer dielectric 3 in a real semi-conductor device are initially calculated. The life estimation for interlayer dielectric 3 is examined by area converting according to the areas of estimated interlayer dielectric 3 and the areas of the interlayer dielectric 3 in a real semi-conductor device. However the TEG with flat structure 30 and the TEG with floating gate transistor structure 40 don""t have a structure in which the floating gate and the interlayer dielectric are separated by a memory cell in a real semi-conductor device. The effect of memory cell structure in a real semiconductor cannot be reflected. The life estimation per bit of the interlayer dielectric 3 is indirectly examined by area converting.
The Japanese Laid-open Patent Publications No. 3-250748 discloses a semi-conductor device that has a device for estimating a film characterization of the insulator film between the floating gate and the control gate. The semiconductor device is used to monitor the film characterization of the insulator film. The accelerated test on the insulator film that has a low probability of defects cannot be performed because the device is useable only for monitoring the film characterization of one insulator film in a cell. If the accelerated test is performed on the insulator film, it is necessary that the areas of the device are enlarged. The accelerated test is therefore indirectly performed by area converting. The estimation is carried out for each memory cell, so that the estimation of the interlayer dielectric 3 tends to be difficultwhere memory cells are arrayed.
Therefore, it is an object of the present invention to provide a semiconductor device with a TEG for estimating an interlayer dielectric that can estimate an effect of floating gate""s structure and the interlayer shape in a real semiconductor device.
Also, it is another object of the present invention to provide a semiconductor with a TEG that can estimate a plurality of interlayer dielectrics in a memory cell array at the same time.
In accordance with one aspect of the present invention, there is provided a semiconductor device with Test Element Group (TEG) for estimating an interlayer dielectric. The semiconductor device with TEG includes a memory cell array. The memory cell array includes a semiconductor substrate, and a floating gate, an interlayer dielectric, and a control gate formed on the substrate in this order. The TEG has a memory cell array similar to the semiconductor device subject to estimation of the interlayer dielectric. The floating gate has an electrode for estimating the interlayer dielectric provided on at least one side against an elongated direction of the memory cell array.
In another aspect of the present invention, the floating gate may be elongated on at least one side against a direction of elongation of the memory cell array for each memory cell.
In a further aspect of the present invention, the floating gate has a dielectric film similar in composition to the interlayer dielectric on the side.
The present invention also provides a process for producing a semiconductor device with TEG for estimating an interlayer dielectric. The process includes the following steps:
S1: forming an isolation on a semiconductor substrate;
S2: forming a floating gate on the semiconductor substrate;
S3: forming an interlayer dielectric on the floating gate;
S4: forming a film for control gate on the interlayer dielectric;
S5: forming a resist pattern on the film for control gate; and
S6: forming a control gate by etching the film for control gate with the resist pattern used as a mask.
Then a memory cell array is constructed by forming the floating gate, the interlayer dielectric, and the control gate formed on the semiconductor substrate in this order.
The step of forming the control gate includes exposing the floating gate by etching the film for control gate. The step of forming the control gate further includes arranging an electrode for estimating the interlayer dielectric on the floating gate, which exists on at least one side against an elongated direction of the memory cell array.
In other aspect of the present invention, the step of forming the control gate includes exposing the floating gate about at least one side against an elongated direction of the memory cell array.
In a yet further aspect of the present invention, the step of forming the control gate includes etching the film for control gate and the interlayer dielectric in this order.
In a yet further aspect of the present invention, the step of forming said control gate may further include of forming a resist pattern and etching the floating gate with the resist or the control gate used as a mask.
The present invention further provides a method of estimating an interlayer dielectric by using the semiconductor device with TEG. The method of estimating an interlayer dielectric includes the following steps.
S1: examining an accelerated life estimation about dielectric breakdown of the interlayer dielectric by certain voltages applied between an electrode provided on the floating gate and an electrode provided on the control gate within a certain time;
S2: detecting the TEG having the dielectric breakdown of the interlayer dielectric within the certain time;
S3: examining a life estimation per bit of the interlayer dielectric, according to the number of bits of the interlayer dielectric included in the TEG having the interlayer dielectric breakdown against the number of bits of the interlayer dielectric included in all Test Element Group.
According to the semiconductor device with TEG of this invention, the TEG has the similar memory cell array to subject to estimation. Therefore the effect of the interlayer dielectric shape, which includes the steps that are occurred by the interlayer dielectric separation, may be examined. The TEG has the memory cell array, so the number of the interlayer dielectric that is included in the TEG having an interlayer dielectric breakdown within the predetermined time can be countable. The life estimation of the interlayer dielectric is examined according to the number of the interlayer dielectric included in the TEG having an interlayer dielectric breakdown against the number of the interlayer dielectric included in all TEG. That is to say, the life estimation per bit of the interlayer dielectric can be directly examined. Since the voltages are applied between a plurality of electrodes provided on the floating gate and the electrode provided on the control gate, the intervals between the electrodes provided on the interlayer dielectric and the floating gate can be reduced. The life estimation can be hardly effected for resistance components of the floating gate.
According to the semiconductor device with TEG of this invention, the floating gate is elongated to at least one side against elongated direction of the memory cell array for each memory cell. Therefore, a plurality of electrodes may be provided on the floating gate easily.
According to the semiconductor device with TEG of this invention, the process for producing the semiconductor device with TEG has no step of removing the interlayer dielectric on the floating gate. Therefore, the semiconductor device with TEG may be simply made.
According to the process of producing the semiconductor device with TEG of this invention, the semiconductor device with TEG may be produced at similar steps of subject to estimation.
According to the process of producing the semiconductor device with TEG of this invention, the floating gate is elongated to at least one side against a direction of elongation of the memory cell array for each memory cell. Therefore, a plurality of electrodes may be provided on the floating gate easily.
According to the process of producing the semiconductor device with TEG of this invention, the interlayer dielectric on the floating gate is etched to remove. Therefore, the electrode may be provided on the floating gate without effect of the interlayer dielectric.
According to the process of producing the semiconductor device with TEG of this invention, the floating gate is formed in a pattern in which the floating gate is elongated to either sides against the memory cell array elongated direction. Therefore, the electrode may be provided on the suitable position of the floating gate.
According to the method of estimating the life estimation of the interlayer dielectric of this invention, the method makes use of the semiconductor device with TEG. The number of the interlayer dielectrics included in the TEG having a dielectric breakdown within the certain time can be countable by bit. Therefore, the life estimation of the interlayer dielectric may be examined according to the ratio of the number of the interlayer dielectric of the dielectric breakdown against the number of the interlayer dielectric included in all TEG. That is to say, the life estimation of the interlayer dielectric can be directly examined per bit, not by area converting.